Senior Analog Layout Engineer
Location: Paris, Europe (Remote)
Salary: Highly Competitive/ Top of Market
Join an innovative technology company focused on advancing AI and semiconductor hardware. Established recently by a team of experts in photonics, electronics, software, mathematics, and machine learning, the company brings together a diverse group of engineers and scientists from top global organizations and research institutions. Operating across multiple international hubs, the company values scientific rigor, fast-paced development, and a collaborative culture.
Role Overview
Lead the design and implementation of high-performance analog and mixed-signal IC layouts, overseeing all phases from floor-planning through to tape-out. Ensure layouts meet stringent requirements for precision, manufacturability, and compliance with foundry specifications.
Responsibilities
• Oversee the layout process for multiple tape-outs, including floor-planning, block and interface definition, and coordination with both internal and external layout engineers.
• Design and implement custom layouts for analog and mixed-signal circuits, including analog and RF components, with a focus on minimizing parasitic effects and maximizing DC and AC signal precision.
• Develop floor-plans and block-level layouts for advanced analog systems.
• Ensure all designs adhere to process design rules and foundry requirements.
• Collaborate with foundry teams to resolve layout-related manufacturing issues.
• Develop and apply custom scripts or tools to automate repetitive layout tasks and improve efficiency.
Required Skills and Experience
• Extensive experience in the physical layout of ADCs, DACs, analog sensing and calibration units, and other mixed-signal components.
• Deep expertise in analog layout techniques, including device matching, parasitic minimization, and noise isolation.
• Proficiency with industry-standard EDA tools (such as Cadence Virtuoso) and workflows for DRC, LVS, and parasitic extraction.
• Experience working with optoelectronic systems and designing TX/RX units for optical circuits is an advantage.
• Familiarity with post-layout simulation using FEM tools (e.g., HFSS) is a plus.
• Experience with layout automation and scripting (e.g., SKILL) is a plus.
• Hands-on experience with medium to advanced semiconductor nodes (<28nm) required.
Pay and Benefits
• Competitive cash compensation, with final package determined by location, experience, and internal equity.
• Early-stage stock option plan participation.
• Relocation assistance and moving expense coverage for candidates relocating near company hubs.
• Comprehensive healthcare (including family options), pension contributions, professional development support, and 25 days of paid time off, plus public holidays.
• Ownership of a key technical domain, with significant opportunities for vertical and horizontal career growth.
• Fast-paced, multicultural, and engineering-driven work environment.