Mixed-Signal IC Design Engineer
Location: Paris, Europe (Remote)
Salary: Highly Competitive/ Top of Market
Join an innovative technology company focused on advancing AI and semiconductor hardware. Established recently by a team of experts in photonics, electronics, software, mathematics, and machine learning, the company brings together a diverse group of engineers and scientists from top global organizations and research institutions. Operating across multiple international hubs, the company values scientific rigor, fast-paced development, and a collaborative culture.
Role Overview
Design, integrate, and deliver high-performance digital subsystems within mixed-signal ICs, supporting control, calibration, and high-speed data transfer in analog-focused environments. Take full ownership of the digital flow from RTL design through to physical implementation and tape-out.
Responsibilities
• Design and verify digital subsystems that interface directly with high-speed analog and mixed-signal circuits, such as calibration engines, control state machines, data converters, and multiplexing logic.
• Integrate and customize external IP blocks (e.g., GPIOs, LVDS I/Os, serial interfaces), ensuring compatibility with analog signal and timing requirements.
• Lead the digital implementation process for mixed-signal blocks, covering RTL, synthesis, floorplanning, place & route, timing closure, physical signoff, and tape-out.
• Collaborate closely with analog, layout, and system teams to co-optimize digital-analog boundaries, address cross-domain issues, and ensure robust high-speed operation.
• Contribute to the development of high-speed serial I/O subsystems; experience with SerDes block design and implementation is a strong plus.
Required Skills and Experience
• Extensive experience in digital RTL design (Verilog/SystemVerilog), especially for mixed- signal systems involving high-speed calibration/control loops, data converters, multiplexers, and serial/parallel data paths.
• Deep understanding of digital-analog integration challenges, including timing closure, noise coupling, clock domain crossing, and analog-aware floorplanning in high-speed environments.
• Demonstrated ability to manage digital blocks through the entire flow: design, verification, synthesis, floorplanning, place & route, and tape-out, particularly within analog or RF ICs.
• Skilled in integrating and adapting external IPs such as GPIOs, LVDS, and serial interfaces (SPI/I²C); experience with high-speed serializers/deserializers (SerDes) is highly valued.
• Proficient with industry-standard EDA toolchains for both front-end (design/verification) and back-end (physical implementation), with a strong understanding of mixed-signal layout constraints.
Pay and Benefits
• Competitive cash compensation, with final package determined by location, experience, and internal equity.
• Early-stage stock option plan participation.
• Relocation assistance and moving expense coverage for candidates relocating near company hubs.
• Comprehensive healthcare (including family options), pension contributions, professional development support, and 25 days of paid time off, plus public holidays.
• Ownership of a key technical domain, with significant opportunities for vertical and horizontal career growth.
• Fast-paced, multicultural, and engineering-driven work environment.